1. Field of the Invention
This invention relates generally to the transfer of data between a communication channel and a host processing system. In particular, the present invention relates to methods for partitioning transactions transferring data from a communication channel to a host system.
2. Description of the Related Art
Many computer systems, such as workstations or personal computers (PCs) with a Pentium® class microprocessor processing device (manufactured by Intel® Corporation, of Santa Clara, Calif.), typically use Peripheral Component Interconnect (PCI) buses as an interconnect transport mechanism to transfer data between different components, such as one or more processors, memory subsystems and input/output (I/O) devices including, for example, keyboards, input mouses, disk controllers, serial and parallel ports to printers, scanners, and display devices. The PCI buses are high performance 32 or 64 bit synchronous buses with slots having automatic configurability and multiplexed address, control and data lines as described in the latest version of “PCI Local Bus Specification, Revision 2.2” set forth by the PCI Special Interest Group (SIG) on Dec. 18, 1998. Currently, PCI slots are the most common connection method used to extend computer systems for add-on arrangements (e.g., expansion cards) with new networking, video, or disk memory storage capabilities. Bridges may be provided to interface and buffer transfers of data to the PCI bus from other subsystems. An example of such a bridge is a PCI-PCI bridge as described in detail in the “PCI-PCI Bridge Architecture Specification, Revision 1.1” set forth by the PCI Special Interest Group (SIG) on Apr. 5, 1995.
The performance of the host processing system may be burdened by the demands of I/O devices to access processors and memory locations of the processing system during data transfer operations. This is especially true for PCI buses with multiple device slots since access to the PCI bus must be acquired before data can be transferred to or from any device connected to the bus. In some systems, such as a server, there may be a large amount of data storage and communications functionality and the demand for access to the system may be complex. For example, data transfers between a processing system and an external communications network are typically highly asynchronous and the bit size of the payload data on the communications channel may not be the same as the bit sizes for host processors, memory subsystems, I/O subsystems, etc. As a result data transfer transactions may not be optimized for external network data, and the wait time for processing data may be unnecessarily lengthened.
Some host processor interfaces and host buses require naturally aligned data. Furthermore, at the beginning of a message sequence, it may be required to know how much data is associated with the message. The amount of data must be specified for the specific naturally aligned granularity of the host processor interface and/or bus. In many cases, the hardware of the network interface does not operate at the same alignment and/or granularity as the host bus and it would be convenient to have a simple efficient mechanism for converting data length counts between naturally aligned granularities.
The host bus may have specific requirements so that data is presented to the processor in a format and in a manner designed for optimum processing speed and throughput. Such requirements necessitate data transactions with specific limitations, such as naturally aligned granularities, address alignment, data alignment, and data length. Thus, data transfers frequently have to be carried out through a number of different transactions. It is preferable that these transactions are partitioned in the most efficient way. There is a need for a method which automatically determines the most efficient partitioning of data transactions.